This invention relates to semiconductor chip packaging and, particularly, to packaging suitable for stacked package modules (such as package-in-package modules).
Semiconductor package substrates typically are laminates of two or more patterned metal layers separated by dielectric layers. Interconnection of the die (one or more, in a stacked die package) to the substrate is made to bond sites in traces in an uppermost metal layer. Interconnection of the package to a motherboard (for example) or to another package in a stacked package module (for example) is made to traces in a lowermost metal layer. Interconnection between upper and lower metal layers is made by vias, which are typically holes in the intervening dielectric layer or layers, filed with conductive material.